Pipelined Fixed-Point FPGA Compute Engine

A hardware acceleration project where I was top contributor to a public multi-contributor repository. The goal was to move a compute-bound render off general-purpose CPU execution and onto an FPGA datapath designed for it.

The pipeline

I implemented a 12-lane Q4.14 fixed-point pipeline reaching 98.2% DSP utilisation at an overclocked 110MHz. Fixed-point rather than floating-point is the decision that makes the rest possible: Q4.14 gives enough range and precision for this workload while keeping each multiply inside a single DSP block, so twelve lanes fit on the fabric and the clock stays high.

Getting to 98.2% DSP utilisation means almost every multiplier on the device is doing useful work every cycle, which is the real measure of whether a pipeline design is sound.

Results

The acceleration path achieves 0.31 Mpx/s at 2K resolution, cutting runtime from 61,878 seconds to 7.10 seconds: an 8,715x improvement, using roughly 3,100 times less energy for the same output.

Getting data on and off the device

Once the compute is fast, the interconnect becomes the bottleneck. The original FastAPI transfer layer was costing about 1 microsecond per byte. I replaced it with a custom binary TCP protocol, bringing that down to 42 nanoseconds per byte, a 96% reduction in frame transfer latency.

Visualisation client

I also built a Unity and C# visualisation client for the team repository, decoding streamed FPGA frames with live parameter control, so the effect of a parameter change is visible immediately rather than after a re-run.